Most digital memory circuits are “single port” memory circuits that can only be read from by a single memory user at a particular time. For example, the well-known standard six-transistor (6T) SRAM memory cell only has a single port for accessing the memory cell. However, for many memory applications it is desirable to have “multi-port” memory circuits where more than one memory user can read from single memory cell at the same time. For example, in a multi-core processor system it is advantageous to allow multiple cores to read from the same memory cell circuit concurrently.
To allow for multiple concurrent memory readers, memory cell circuits may be altered to include additional memory ports for accessing the memory cell circuit. For example, the standard six-transistor (6T) single-port SRAM memory cell can be made into an eight-transistor (8T) two-port memory cell by adding two more transistors that provide a second port for accessing the memory cell circuit. However, simply adding another physical port to a memory cell circuit introduces a few disadvantages.
A first problem with adding two additional port transistors to a 6T single-port SRAM memory cell circuit to create an 8T two-port SRAM memory cell is that adding two more transistors to the memory cell circuit increases the size of the memory cell circuit. Increasing the size of the memory cell circuit will reduce the memory density and thus reduce the amount of memory that can be manufactured in a defined area. Furthermore, due to the risk of losing the stored data bit during a read of the SRAM memory cell, certain transistors in the 8T SRAM memory cell must be made much larger thus further increasing the size of the 8T two-port SRAM memory cell. The same technique of adding additional port transistors can be used to create three-port memory cells, four-port memory cells, or memory cells with even higher numbers of ports.
As a result of adding additional transistors, multi-port memory cells tend to have very low memory density characteristics. Furthermore, the additional transistors will consume power such that multi-port memory systems consume more power than single-port memory systems. Therefore, it would be desirable to have alternative designs for multi-port memory cells.